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| quad non-programmable pcm codec idt821024 1 the idt logo is a registered trademark of integrated device technology, inc industrial temperature range february 9, 2009 ? 2003 integrated device technology, inc. dsc-6034/4 fea tures 4 channel codec with on-chip digital filters selectable a-law or m -law companding master clock frequency selection: 2.048 mhz, 4.096 mhz or 8.192 mhz - internal timing automatically adjusted based on mclk and frame sync signal separate pcm and master clocks single pcm port with up to 8.192 mhz data rate (128 time slots) transhybrid balance impedance hardware adjustable via external components transmit gains hardware adjustable via external components low power +5.0 v cmos technology +5.0 v single power supply package available: 32 pin plcc, 44 pin tqfp functional block diagram anolog front end ch2 anolog front end ch1 anolog front end ch3 anolog front end ch4 dsp pcm interface pcm tsa 1 pcm tsa 2 pcm tsa 3 pcm tsa 4 clock & reference circuits control pdn 1~ 4 a /m iin1 vout1 iin2 vout2 iin3 vout3 iin4 vout4 mclk iref cnf fsx1 fsr1 fsx2 fsr2 fsx3 fsr3 fsx4 fsr4 dx tsc dr pclk vcca agnd vccd dgnd description the idt821024 is a single-chip, four channel pcm codec with on- chip filters. the device provides analog-to-digital and digital-to-analog conversions and supports both a-law and m- law companding. the digital filters in idt821024 provides the necessary transmit and receive filtering for voice telephone circuit to interface with time-division multiplexed systems. all of the digital filters are performed in digital signal processors operating from an internal clock, which is derived from mclk. the fixed filters set the transmit and receive gain and frequency response. in the idt821024 the pcm data is transmitted to and received from the pcm highway in time slots determined by the individual frame sync signals (fsr n and fsx n , where n = 1-4) at rates from 256 khz to 8.192 mhz. both long and short frame sync modes are available in the idt821024. the idt821024 can be used in digital telecommunication applications such as pbx, central office switch, digital telephone and integrated voice/ data access unit.
2 industrial temperature range idt821024 quad non-programmable pcm codec pin configura tions 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4 3 2 1 32 31 30 32-pin plcc vout4 a/ m fsx4 fsr4 fsx3 fsr3 fsx2 vout1 cnf pdn1 pdn2 pdn3 pdn4 mclk 29 28 27 26 25 24 23 22 21 pclk tsc dgnd dx vccd dr fsr1 fsx1 fsr2 iin1 iin2 vout2 vcca iref agnd vout3 iin3 iin4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 44-pin tqfp iin4 vout4 nc nc a/ m nc fsx4 fsr4 fsx3 fsr3 fsx2 iin1 vout1 nc cnf nc pdn1 pdn2 pdn3 pdn4 mclk pclk 33 32 31 30 29 28 27 26 25 24 23 nc nc tsc dgnd nc dx vccd dr fsr1 fsx1 fsr2 iin2 vout2 nc nc vcca iref agnd nc nc vout3 iin3 3 industrial temperature range idt821024 quad non-programmable pcm codec pin description pin number name i/o plcc tqfp description agnd -- 10 7 analog ground. all ground pins should be connected to the ground plane of the circuit board . vcca -- 8 5 +5 v analog power supply. all power supply pins should be connected to the power plane of the circuit board. dgnd -- 27 30 digital ground. all ground pins should be connected to the ground plane of the circuit board . vccd -- 25 27 +5 v digital power supply. all power supply pins should be connected to the power plane of the circuit board. dr i 24 26 receive pcm data input. the pcm data for channel 1, 2, 3 and 4 is shifted serially into dr pin by the receive frame sync signal (fsr) with msb first. a byte of data for each channel is received every 125 m s at the pclk rate. dx o 26 28 transmit p cm data output. the pcm data for channel 1, 2, 3 and 4 is shifted serially out to the dx pin by the transmit frame sync signal (fsx) with msb first. a byte of data for each channel is transmitted every 125 m s at the pclk rate. dx is high impedance between time slots. fsr1 fsr2 fsr3 fsr4 i 23 21 19 17 25 23 21 19 receive frame sync input for channel 1/2/3/4 this 8khz signal pulse identifies the receive time slot for channel n on a system?s receive pcm frame. it must be synchronized to pclk. fsx1 fsx2 fsx3 fsx4 i 22 20 18 16 24 22 20 18 transmit frame sync input for channel 1/2/3/4 this 8 khz signal pulse identifies the transmit time slot for channel n on a system?s transmit pcm frame. it must be synchronized to pclk. iref o 9 6 reference current. the iref output is biased at the internal reference voltage. a resistor placed from iref to ground sets the reference current used by the analog - to - digital converter to encode the signal current present on iinn pin (n is channel number, n = 1 to 4) into digital for m. vout1 vout2 vout3 vout4 o 4 7 11 14 43 2 10 13 voice frequency receiver output for channel 1/2/3/4 this is the output of receiver amplifier for channel n. the received digital data from dr is processed and converted to an analog signal at this pin. ii n1 iin2 iin3 iin4 i 5 6 12 13 44 1 11 12 voice frequency transmitter input for channel 1/2/3/4 this is the input to the gain setting amplifier in the transmit path for channel n. the analog voice band voltage signal is applied to this pin through a resisto r. this input is a virtual ac ground input, which is biased at the iref pin. mclk i 30 35 master clock. the master clock provides the clock for the dsp. it can be either 2.048 mhz or 4.096 mhz. the idt821024 determines the mclk frequency via the fsx input s and makes the necessary internal adjustments automatically. the mclk frequency must be an integer multiple of the fsx frequency. pclk i 29 34 pcm clock. the pcm clock shifts out the pcm data to the dx pin and shifts in pcm data from the dr pin. the pcm clock frequency is an integer multiple of the frame sync frequency. when pclk is connected to mclk, the pcm clock can generate the dsp clock as well. tsc o 28 31 time slot control. this open drain output is low active. when the pcm data is transmitted to the dx pin for any of the four channels, this pin will be pulled low. a/ m i 15 16 a/ m - law selection. when this pin is low, m - law is selected; when this pin is high, a - law is selected. this pin can be connected to vccd or dgnd pin directly. 4 industrial temperature range idt821024 quad non-programmable pcm codec pin number name i/o plcc tqfp description pdn1 pdn2 pdn3 pdn4 i 2 1 32 31 39 38 37 36 channel 1/2/3/4 power down. when this pin is high, channel n is powered down. cnf o 3 41 capacitor for noise filter. this pin should be connected to agnd through a 0.1 m f capacitor. nc -- 3, 4, 8, 9, 14, 15, 17, 29, 32, 33, 40, 42 no connection pin description ( cont?d ) 5 industrial temperature range idt821024 quad non-programmable pcm codec functional description the idt821024 contains four channel pcm codec with on chip digital filters. it provides the four-wire solution for the subscriber line circuitry in digital switches. the device converts analog voice signal to digital pcm data, and converts digital pcm data back to analog signal. digital filters are used to bandlimit the voice signals during the conversion. either a-law or m -law is supported by the idt821024. the law selection is performed by a/ m pin. the frequency of the master clock (mclk) can be 2.048 mhz, 4.096 mhz, or 8.192 mhz. internal circuitry determines the master clock frequency automatically. the serial pcm data for four channels are time multiplexed via two pins, dx and dr. the time slots of the four channels are determined by the individual frame sync signals at rates from 256 khz to 8.192 mhz. for each channel, the idt821024 provides a transmit frame sync signal and a receive frame sync signal. each channel of the idt821024 can be powered down independently to save power consumption. the channel power down pins pdn1-4 configure channels to be active (power-on) or standby (power-down) separately. signal processing high performance oversampling analog-to-digital converters (adc) and digital-to-analog converters (dac) are used in the idt821024 to provide the required conversion accuracy. the associated decimation and interpo- lation filtering are realized with both dedicated hardware and digital signal processor (dsp). the dsp also handles all other necessary functions such as pcm bandpass filtering and sample rate conversion. transmit signal processing in the transmit path, the analog input signal is received by the adc and converted into digital data. the digital output of the oversampling adc is decimated and sent to the dsp. the transmit filter is implemented in the dsp as a digital bandpass filter. the filtered signal is further decimated and compressed to pcm format. transmit pcm interface the transmit pcm interface clocks out 1 byte (8 bits) pcm data out of dx pin every 125 m s. the transmit logic, synchronized by the transmit frame sync signal (fsxn), controls the data transmission. the fsxn pulse identifies the transmit time slot of the pcm frame for channel n. the pcm data is transmitted serially on dx pin with the most significant bit (msb) first. when the pcm data is being output on dx pin, the tsc signal will be pulled low. receive signal processing in the receive path, the pcm code is received at the rate of 8,000 samples per second. the pcm code is expanded and sent to the dsp for interpolation. a receive filter is implemented in the dsp as a digital lowpass filter. the filtered signal is then sent to an oversampling dac. the dac output is post-filtered and delivered at vout pin by an amplifier. the amplifier can drive resistive load higher than 2 k w . receive pcm interface the receive pcm interface clocks 1 byte (8 bits) pcm data into dr pin every 125 m s. the receive logic, synchronized by the receive frame sync signal (fsrn), controls the data receiving process. the fsrn pulse identifies the receive time slot of the pcm frame for channel n. the pcm data is received serially on dr pin with the most significant bit (msb) first. hardware gain setting in transmit path the transmit gain of the idt821024 for each channel can be set by 2 resistors, r ref and r txn (as shown in figure 1), according to the follow- ing equation: txn ref t r r 3 g = the receive gain of idt821024 is fixed and equal to 1. a/d i ref v ref to i ref v ref d/a bal net r ref 1 i ref 1 v ref 1 c fil v in 1 v out 1 idt821024 c tx 1 r tx 1 r rx 1 c rx 1 to slic rsn to slic vtx figure 1. idt821024 transmit gain setting for channel 1 6 industrial temperature range idt821024 quad non-programmable pcm codec operating the idt821024 the following descriptions about operation applies to all four channels of the idt821024. power-on sequence and master clock configuration to power on the idt821024 users should follow this sequence: 1. apply ground; 2. apply vcc, finish signal connections; 3. set pdn1-4 pins high, thus all of the 4 channels are powered down; the master clock (mclk) frequency of idt821024 can be configured as 2.048 mhz, 4.096 mhz or 8.192 mhz. using the transmit frame sync (fsx) inputs, the device determines the mclk frequency and makes the necessary internal adjustments automatically. the mclk frequency must be an integer multiple of the frame sync frequency. operating modes there are two operating modes for each transmit or receive channel: standby mode (when the channel is powered down) and normal mode (when the channel is powered on). the mode selection of each channel is done by its corresponding pdn pin. when pdnn is 1, channel n is in standby mode; when pdnn is 0, channel n is in normal mode. in standby mode, all circuits are powered down with the analog outputs placed in high impedance state. in normal mode, each channel of the idt821024 is able to transmit and receive both pcm and analog information. the normal mode is used when a telephone call is in progress. companding law selection an a/ m pin is provided by idt821024 for the companding law selection. when this pin is low, m -law is selected; when the pin is high, a-law is selected. 7 industrial temperature range idt821024 quad non-programmable pcm codec analog interface absol ute maximum ra tings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. power dissipation recommended dc opera ting conditions note: mclk: 2.048 mhz, 4.096 mhz or 8.192 mhz with tolerance of 50 ppm rating com?i & ind?i unit power supply voltage 6.5 v voltage on any pin with respect to ground -0.5 to 5.5 v package power dissipation 600 mw storage temperature -65 to +150 c parameter min. typ. max. unit operating temperature - 40 +85 c power supply voltage 4.75 5.25 v digital interface electrical chara cteristics parameter description min typ max units test conditions v il input low voltage 0.8 v all digital inputs v i h input high voltage 2.0 v all digital inputs 0.4 v dx, tsc , i l = 14 ma 0.8 v all other digital outputs, i l = 4 ma . v o l output low voltage 0. 2 v all digital pins, i l = 14 ma vdd - 0.6 v dx, i h = - 7 ma , all other outputs, i h = - 4 ma v oh output high voltage vdd - 0.2 v all digital pins, i h = - 1 ma i i input current - 10 10 m a any digital input s gnd 9 industrial temperature range idt821024 quad non-programmable pcm codec distortion noise parameter description min typ max units test conditions std x transmit signal to total distortion ratio a - law : input level = 0 dbm0 input level = - 30 dbm0 input level = - 40 dbm0 input level = - 45 dbm0 m - law : input level = 0 dbm0 input level = - 30 dbm 0 input level = - 40 dbm0 input level = - 45 dbm0 36 36 30 24 36 36 31 27 db db db db db db db db itu - t o.132 sine wave method,psophometric weighted for a - law, c message weighted for m - law. std r receive signal to total distortion ratio a - law : inp ut level = 0 dbm0 input level = - 30 dbm0 input level = - 40 dbm0 input level = - 45 dbm0 m - law : input level = 0 dbm0 input level = - 30 dbm0 input level = - 40 dbm0 input level = - 45 dbm0 36 36 30 24 36 36 31 27 db db db db db db db db itu - t o.1 32 sine wave method,psophometric weighted for a - law;sine wave method,c message weighted for m - law; sfd x single frequency distortion, transmit - 42 dbm0 200 hz - 3400 hz, 0 dbm0 input, output any other single frequency 3400 hz sfd r single frequency di stortion, receive - 42 dbm0 200 hz - 3400 hz, 0 dbm0 input, output any other single frequency 3400 hz imd intermodulation distortion - 42 dbm0 transmit or receive,two frequencies in the range (300 hz - 3400 hz) at - 6 dbm0 parameter description min typ max units test conditions n xc transmit noise, c message weighted for m - law 16 dbrnc0 n xp transmit noise, psophometric weighted for a - law - 68 dbm0p n rc receive noise, c message weighted for m - law 12 dbrnc0 n rp re ceive noise, psophometric weighted for a - law - 78 dbm0p n rs noise, single frequency f = 0 khz ? 100 khz - 53 dbm0 iin = 0 a, tested at vout psr x power supply rejection transmit f = 300 hz ? 3.4 khz f = 3.4 khz ? 20 khz 40 25 db db vdd = 5.0 vdc + 100 mvrms psr r power supply rejection receive f = 300 hz ? 3.4 khz f = 3.4 khz ? 20 khz 40 25 db db pcm code is positive one lsb, vdd = 5.0 vdc + 100 mvrms sos spurious out - of - band signals at v out relative to input pcm code applied: 4600 hz ? 20 kh z 20 khz ? 50 khz - 40 - 30 db db 0 dbm0, 300 hz ? 3400 hz input 10 industrial temperature range idt821024 quad non-programmable pcm codec interchannel crosstalk intrachannel crosstalk parameter description min typ max units test conditions xt x - r transmit to receive crosstalk - 85 - 78 db 300 hz ? 3400 hz, 0 dbm0 signal into iin of interfering channel. idle pcm code into channel under test. xt r - x receive to transmit crosstalk - 85 - 80 db 300 hz ? 3400 hz, 0 dbm0 pcm code into interfering channel. iin = 0 a for channel under test. xt x - x transmit to transmit crosstalk - 85 - 78 db 300 hz ? 3400 hz, 0 dbm0 signal into iin of interfering channel. iin = 0 a for channel under test. xt r - r r eceive to receive crosstalk - 85 - 80 db 300 hz ? 3400 hz, 0 dbm0 pcm code into interfering channel. idle pcm code into channel under test. parameter description min typ max units test conditions xt x - r transmit to receive crosstalk - 80 - 70 db 300 hz ? 3400 hz, 0 dbm0 signal into iin. idle pcm code into dr. xt r - x receive to transmit crosstalk - 80 - 70 db 300 hz ? 3400 hz, 0 dbm0 pcm code i nto dr. iin = 0 a. 11 industrial temperature range idt821024 quad non-programmable pcm codec timing characteristics clock parameter description min typ max units test conditions t1 pclk duty cycle 40 60 % pclk=512khz to 8.192mhz t2 pclk rise and fall time 25 ns pclk=512khz to 8.192mhz t3 mclk duty cycle 40 60 % mclk=2.048hz,4.096mhz or 8.192mhz t4 mclk rise and fall time 15 ns mclk=2.048hz,4.096mhz or 8.192mhz t5 pclk clock period 244 ns pclk=512khz to 8.192mhz transmit parameter description min typ max units test conditions t11 data output delay time (for short frame sync mode) 5 70 ns t12 data hold time 5 70 ns t13 data delay to high-z 50 220 t5+70 ns t14 frame sync hold time 50 ns t15 frame sync high setup time 55 t5-50 ns t16 tsc enable delay time(for short frame sync mode) 5 80 ns t17 tsc disable delay time 50 220 t5+70 ns t18 data output delay time(for long frame sync mode) 5 40 ns t19 tsc enable delay time(for long frame sync mode) 5 40 ns t21 receive data setup time 25 ns t22 receive data hold time 5 ns figure 2. mclk timing note: timing parameter t13 is referenced to a high-impedance state. mclk t4 t4 12 industrial temperature range idt821024 quad non-programmable pcm codec figure 3. pcm interface timing for short frame mode figure 4. pcm interface timing for long frame mode 1 2 3 4 5 6 7 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 pclk fsx/ fsr dx dr t15 t14 t2 time slot t2 t13 t12 t11 t21 t22 tsc t16 t17 t5 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 1 2 3 4 5 6 7 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 pclk fsx/ fsr dx dr t15 time slot t2 t13 t12 t18 t21 t22 tsc t19 t17 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 1 t2 t5 13 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1552 santa clara, ca 95054 fax: 408-492-8674 email: telecomhelp@idt.com www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. data sheet document history 01/16/2002 pgs. 4, 5 02/21/2002 pgs. 1-4, 13 09/10/2002 pg. 8 01/08/2003 pgs. 1, 13 04/03/2003 pg. 1 02/09/2009 pg. 13 removed idt from orderable part number xxxxxx xx x device type blank process/ temperature range j 821024 industrial (-40 c to +85 c) plastic leaded chip carrier (plcc, pl32) quad non-programmable pcm codec package pp thin quad flat pack (tqfp, pp44) ordering informa tion |
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